ABSTRACT
This paper presents a dual transition preferentially sized (DTPS) logic that uses two separate paths—one for the fast propagation of low-to-high signal and the other for fast propagation of high-to-low signal. DTPS logic is suitable for multistage buffers and critical sections of data paths requiring good noise immunity and low power dissipation while achieving high performance.
The need of DTPS logic arises from the fact that there are multistage buffers and critical sections of data path which require good noise immunity, low propagation delay and low power dissipation with no degradation in performance. All this criteria is not met by TTL, CMOS and Domino logic.
This paper derives formulas to obtain optimal tapering factors of multistage buffers based on preferentially sized (PS) inverters, and implemented DTPS logic using the optimal tapering factors. Also data paths based on static CMOS logic, domino logic, and DTPS logic in 0.18- m technology are fabricated. DTPS logic shows 15% and 16% improvements in performance and power dissipation, respectively, over domino, and 42% improvement in performance compared to static CMOS.
INTRODUCTION
The main factors what designer will look into while designing as digital circuit are
(i) The circuit should have low propagation delay (i.e., his circuit should be faster).
(ii) The circuit should only consume less power (i.e., power dissipation should be less).
(iii) The circuit should be immune to noise interferences (i.e. noise immunity should be high).
(iv) The overall performance of the circuit will be high.(i.e. Efficiency should be high)
With the scaling of process technology, high performance and low power consumption are becoming important
issues in circuit design. The use of domino circuits is one way to alleviate the problem of high-performance circuit design. However, domino circuits consume more power than standard CMOS logic, and are susceptible to noise (for scaled technologies with low transistor threshold voltage) because in the evaluation mode intermediate nodes may be floating.
Domino logic circuit techniques are extensively applied in high- performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to static CMOS circuits. High-speed operation of domino logic circuits is primarily due to the lower noise margins of domino circuits as compared to static gates. This desirable property of a lower noise margin, however, makes domino logic circuits highly sensitive to noise as compared to static gates. As on-chip noise becomes more severe with technology scaling and increasing operating frequencies, error free operation of domino logic circuits has become a major challenge.
In order to achieve good noise immunity and low power consumption while achieving performance comparable to domino logic, we propose dual transition preferentially sized (DTPS) logic, which consists of dual monotonic data paths (one is fast for rising transition of input, and the other is for falling transition) using preferentially sized (PS) circuits . Since a PS inverter chain uses up-sized
inverters and down-sized inverters alternately to speed up data propagation in evaluation cycle, the ratio of output capacitance to input capacitance of even stages of multistage PS buffers is different from that of odd stages. Hence, different tapering factors should be used for even and odd stages, which are also different from the tapering factor of normal inverter chains. This paper derives formulas for optimal tapering factors of multistage buffers based on PS inverters to minimize the propagation delay. DTPS is implemented based on PS inverter chains using dual tapering factors. DTPS logic is not only suitable for multistage buffers but also ideal for critical sections of data paths requiring high performance and low power consumption. This paper also describes how to design DTPS logic using a high sizing ratio in critical paths of design to achieve a very high performance. Data paths based on static CMOS logic, domino logic, and DTPS logic are fabricated. The measurement results show the advantages of DTPS logic.
PREFERENTIALLY SIZED (PS) LOGIC
As circuit integration increases, demand for high performance buffers drive large capacitive loads also increases. One of the solutions to this need is to use a multi-stage PS buffer. Then, in order to minimize the delay due to inserting PS buffers, the optimal tapering factor and the number of stages should be derived.
The circuit topology of PS logic is the same as that of static CMOS logic. However, the PMOS or the NMOS are preferentially sized to achieve fast high-to-low transition or low to high transition. For example, to speed up high-to-low transition, the NMOS transistors are sized up while the PMOS are reduced.
In order to design high performance multistage buffers and data paths using DTPS logic proposed in this paper, we first consider PS buffers that are the building blocks of the DTPS buffers. Then, in order to minimize the delay due to the PS buffers, optimal tapering factors are considered, which are different from the tapering factor of normal inverter chains. Fig. 1 shows some examples of how to adjust the sizes of PS circuit style, where s is the sizing ratio and ยต is the ratio of optimal size of the PMOS to NMOS in a static CMOS inverter. And b is the tapering factor, which is the ratio of output capacitance to the input capacitance of an inverter. The arrows represent the sizing directions of the inverters. In this paper we used sizing ratios greater than 1. Since a multistage PS buffer uses up-sized inverters and down-sized inverters alternately, we should use two tapering factors for a multistage PS buffer—one for the even stages and the other for the odd stages.
DUAL TRANSITION PREFERENTIALLY SIZED (DTPS) LOGIC
This paper propose to use DTPS logic, in which the sizes of PS inverters on each data path are determined based on the optimal tapering factors, to achieve high performance and low power dissipation. DTPS logic does not require a clock signal.
DTPS logic consist of dual monotonic data paths (one for fast propagation of low to high transition and the other for high to low transition) using preferentially sized (PS) circuits and a combiner that detect the earliest transition, latches it, and then transfers the data to the next stage. Hence the propagation delay due to the high to low transition is same as that of the low to high transition of the input, i.e., the propagation delay of DTPS logic in pre charge cycle is same as that
of the evaluation cycle. Since DTPS logic does not require any additional clock signal to pre-charge the gates during pre charge cycle, and has no floating node in the evaluation mode, it has good noise immunity and achieves low power consumption while achieving performance comparable to Domino logic. DTPS logic not only suitable for multi-stage buffers but also ideal for critical sections of data paths requiring high performance and low power consumption. This paper also concentrates on the design methodologies of critical data paths using the DTPS logic.
PROBLEMS IN DTPS LOGIC
Since the top path is duplicated in the bottom path the total layout area will increase in DTPS Logic. This a really a draw back because the layout area should be minimum in designing processor circuits etc.
The other drawback is since multiple input gates are used in DTPS logic the fan in of individual gates will be more. Fan in will become while fabricating IC’s based on DTPS Logic.
SOLUTION TO PROBLEMS IN DTPS LOGIC
We can partition combinational gates on each data path into two parts: gates having a critical input signal and gates having no critical input signals. For example, in Fig. 6, a 4-input NAND gate (G1) on the top data path can be partitioned into 2-input NAND gate (G3) and 3-input NOR gate (G5), and G2 on bottom data path can also be partitioned into G4 and G5. Since G5 is common, it can be shared as shown in Fig. 6(b). Gates G3 and G4 are on the critical paths; however, G5 is on the non critical path. Logic restructuring reduces gate fan-in and the size of transistors on the critical paths, which decreases load capacitance on the critical paths, thereby reducing the delay and the layout area.
So by partitioning the multi input in individual gates in DTPS logic to 2 input or 3 input gates will reduce the fan in of gates. Also partitioning will reduce the size of transistors to be fabricated on the critical data paths. So by partitioning gates the overall layout area of the DTPS Logic can be reduced.
CONCLUSION
This paper proposed Dual Transition Preferentially Sized (DTPS) logic, which is suitable for multistage buffers and critical sections of data paths requiring a very high performance with low power consumption. Expressions for optimal tapering factors of multistage buffers based on PS inverters are derived to minimize the propagation delay. Analytical results show that PS buffers with dual tapering factors can achieve up to 13% performance improvement over ones using one tapering factor. For the Preferentially Sized (PS) buffers using dual tapering factors, the difference between the analytical results and the simulation results is less than 10%. Test chip for data paths based on DTPS logic, static CMOS, and Domino logic are fabricated and measured results shows 15% and 16% improvements in performance and power, respectively, over Domino and 42% delay improvement over the static CMOS logic.
The limitation of DTPS logic over the other (static CMOS and Domino logic) is the DTPS logic requires more area for fabrication since it is duplicating the data paths. Hence we can conclude that DTPS logic is the best suited technology for constructing digital circuits which require multistage buffers and critical data paths.
REFERENCE
(i) IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2,
FEBRUARY 2005 “High-Performance Low-Power Dual
Transition Preferentially Sized (DTPS) Logic”
Woopyo Jeong and Kaushik Roy, Fellow, IEEE
(ii) J. M. Rabaey, Digital Integrated Circuits: A Design Perspective,
(iii) C. Prunty and L. Gal, “Optimum tapered buffer,” IEEE J. Solid-
State Circuits, vol. 27, no. 1, pp. 118–119, Jan. 1992.
(iv) www.purdue.edu
(v) www.cparity.com